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Understanding Pipelining and Superscalar Execution
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Posted by: TotalRecall
ArsTechnica has posted Part II of their series on Understanding the Microprocessor, Understanding Pipelining and Superscalar Execution. Here's a snip:
To return to our assembly line analogy, each of the above stages could be said to represent one stage in the life-cycle of an instruction. An instruction starts out in the fetch stage, moves to the decode stage, then to the execute stage, and finally to the write stage. Early processors were like our first, inefficient assembly line: there was only one instruction in the pipeline at a time, and as the instruction moved to each successive stage all of the other stages would lie idle. The result of this was that if each stage took 10 ms to complete, then the processor could finish only one instruction every 40 ms.
Read on here.
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