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Facts and Assumptions about the Opteron and Athlon 64
(Click here to view the original thread with full colors/images)
Posted by: TotalRecall
Digit-Life has written an article on AMD's upcoming Hammer based chips, the Athlon 64 and Opteron:
The L2 to L1 data transfer rate is increased twice (compared with the Athlon XP) - it must boost the perofrmance in many operations. But how? by extending the bus or reducing the access delays? Most likely, it's the bus extension because we need at least 128 bits in the 64bit mode for simultaneous delivery of an instruction and an operand. Or it became possible to conduct two simultaneous operations of data transfer, for example, writing and reading, which is equivalent to an increase of the effective bus bandwidth. Besides, the L2 cache supports delayed requests - 8 delayed requests for data and 2 for instructions. As usual, several buffers are supported: a victim buffer for 8 inputs, snoop buffer of the same size and a write buffer for 4 inputs.
Check it out here.
Source: AnandTech
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