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Volume Multi-Processor Systems: Part 3
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Posted by: TotalRecall
If you have been following Ace's Multi-Processor Systems series, they have posted part three:
Welcome to the third and final part of Volume Multi-Processor Systems, a series generally concentrating on current and upcoming two to eight-way multi-processor systems. In the first part, we covered uniprocessor performance, workstation and server sizing, and CPU and system design considerations. For Part 2, we took a look at the specific architectural implementations of several volume multi-processor systems, including those based around the Pentium III, Pentium 4, Athlon, PowerPC, Itanium, and UltraSPARC architectures. We also covered architectural improvements in CPUs due to appear in the future, including integrated northbridges/memory controllers and improvements in thread-level parallelism (TLP) through on-chip multiprocessing (CMP) and fine-grained multithreading. This time around, we’ll take a look into the future of volume multi-processor systems (or the very immediate present in the case of the recently introduced Itanium 2). Of course, we’ll look at the significantly improved SPECfp2000-leading Itanium 2, Sun’s “low-end” UltraSPARC IIIi with on-board 128-bit DDR SDRAM memory controller and 1 MB L2 cache, and the first 64-bit x86 processor: AMD’s Opteron. I’ll also be discussing some more general trends of the market as well as making some observations of customer and vendor requirements alike. Finally, there will be an overview of where all the major CPU architectures and companies are at the moment and where they’re going.
Read it here.
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